The present invention relates to a non-destructive method for detecting failure in a flip-chip module and a system therefore, and more specifically, to a non-destructive method for detecting delamination and crack propagation in a flip-chip module and a system.
Flip-chip technology includes methods for interconnecting semiconductor devices, such as integrated circuit (IC) chips to external circuitry using solder bumps that have been deposited onto chip pads. The solder bumps are deposited on the chip pads on a top side of a wafer to mount the chip to external circuitry (e.g., a circuit board or another chip or wafer). The wafer is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is flowed to complete the interconnect. This technique is in contrast to wire bonding, in which the chip is mounted upright, and wires are used to interconnect the chip pads to external circuitry.
Flip chip assembly technology, wherein the integrated circuit chips are essentially flipped over and bonded to substrates using solderable interconnects, has seen rapid growth in semiconductor packaging in recent years. Alignment marks on the chip and the fiducial marks on the substrates are used for the fast automatic alignment between the chip and the substrate using a flip chip tool. The assembly of encapsulated flip chip circuit boards, however, remains a time consuming and expensive process. The key drivers for the demand for this technology are increased I/O connections enabling greater speed and shorter connections resulting in improved signal integrity.
In order for wafer level packaging to be successful, the flip chip tool must be able to align the integrated circuit chips (also referred to as a die) to the substrate. Normally, key features on the die and substrate are located using vision systems. These points are used as references in the alignment of the die and the substrate. Key features on the die are either fiducials or solder bumps. Key features on the substrate are either fiducials or bond pads. Two or more die may be stacked in a single package.
An integrated circuit substrate may comprise a number of layers. Some layers may comprise organic or ceramic dielectric material. Some layers may comprise conductors, such as traces, ground planes, and vias. An IC substrate may include an electronic component mounted on a surface of the substrate. The electronic component may be functionally connected to other elements of an electronic system through a hierarchy of conductors that include substrate traces, ground planes, and vias. The conductors may carry signals that are transmitted among the electronic components, such as integrated circuits, of the system. An integrated circuit substrate may have a relatively large number of input/output (“I/O”) terminals (also called “lands”), as well as a large number of power and ground terminals or lands, on a surface of the integrated circuit substrate. An integrated circuit can include a lid which makes failure analysis like de-lidding and cross-sectioning irreversible/destructive.
The underfill material, which occupies the space between the flipped integrated circuit chip and the integrated circuit substrate, is important for reliability of the flip chip packages. Underfill material supports the electrical connections, protects them from the environment, and reduces the thermomechanical stress on the flip chip connection. The main reason for the thermal mechanical stress is the difference in coefficients of expansion (CTE) between the silicon chip and the organic laminate. For example the coefficient of thermal expansion of the silicon chip can be 1.0 to 15.0 parts per million per degrees Celsius (ppm/° C.) and the CTE for the organic laminate can be 12 to 25 ppm/° C. The CTE underfill material can be targeted to be close to the CTE of the solder interconnect which can be 22 ppm/° C. (low lead and lead free solders) to 28 ppm/° C. (high lead solders). The high modulus of elasticity (8 to 12 GigaPascals (GPa)) of the underfill material rigidly links the silicon and laminate over the entire area of the silicon and distributes the CTE mismatched thermal mechanical stress between silicon and laminate over the entire bonded area, rather than allowing the thermal mechanical stress to be concentrated at the solder joint, and cause fatigue fracture. In order to reduce this CTE mismatch, underfill materials typically contain inorganic filler, such as silica. Generally, the higher concentration of inorganic filler in the underfill material, the higher the thermal conductivity, which is desirable for high heat transfer so as to remove heat during operation of the chips.
It can be desirable to monitor the flip-chip module for failure causes by crack propagation or delamination of the underfill material before catastrophic failure without destroying the flip-chip module. Current methods include confocal mode scanning acoustic microscopy, electrical readout and probing of the controlled collapse chip connections, and destructive physical failure analysis by cross-sectioning the module. However, by the time the controlled collapse chip connection resistance has increased to the failure criteria, the damage in the module is so extensive that a root cause of the failure cannot be resolved. In fact, each of these methods fails to provide early failure detection or meaningful granularity for analysis or feedback. These methods are also time consuming, lab-intensive, expensive and/or destructive. These methods ultimately require more parts for stress qualification coming at a high cost with a large reliance on model assumptions.